An image sensor captures an image by using a semiconductor device's feature of reacting to external energy, for example, photons. Light generated from an object existing in nature has an intrinsic energy value in a wavelength thereof. A pixel of the image sensor detects the light generated from the object and converts the detected light to an electric value.
FIG. 1 is a timing diagram of driving an image sensor using a 4-transistor CMOS active pixel, in which data is read out in a correlated double sampling (CDS) method. FIG. 2 is a view illustrating the conventional 4-transistor CMOS active pixel to explain a section of a photodiode and an electronic potential for each area based on the timing diagram of FIG. 1.
Referring to FIG. 2, the 4-transistor CMOS active pixel includes a transmission transistor 11 to connect a photodiode area A1 and a floating diffusion node area A3, and a reset transistor 13 to initialize the photodiode area A1. A photodiode PH is formed to a predetermined depth from a surface of a semiconductor which is a dark current source, to reduce dark current. Thus, a potential wall or a potential well is formed in a portion K to connect the transmission transistor 11 and the photodiode PH according to the state of injection of a semiconductor impurity.
Since the potential well characteristically makes electric charges remain as they are, most semiconductor manufacturing companies manufacture pixels in the form of the potential wall while excluding the potential well form. Also, semiconductor manufacturing companies have developed to improve a process to minimize the potential wall. However, since the size of the potential wall varies according to a difference in processing conditions, it is very difficult to remove the potential wall with a processing technology.
As the potential wall is larger, the amount of electric charges which do not move to the floating diffusive node FD and remain in the photodiode pH increases so that a dead region of an image sensor increases. The increase of the dead region is more remarkable when data is read out by using the correlated double sampling method as shown in FIG. 1. In FIG. 1, a reset sampling signal RSH is a signal to sample and store reset data, i.e., an electric potential in the initial state of a floating diffusive node FD. A signal sampling signal DSH is a signal to sample and store signal data, i.e., an electric potential of the floating diffusive node after charges generated from the photodiode PH are received.
In the electronic potential shown in FIG. 2, a solid line n1 indicates an electronic potential in a state in which the transmission transistor 11 and the reset transistor 13 are all turned on, that is, in a reset section of FIG. 1. As it can be seen by the solid line n1 in FIG. 2, even when the transmission transistor 11 and the reset transistor 13 are all turned on, a predetermined amount of extra charges remain in the photodiode area A1 by the potential wall w1 formed at a boundary surface K between the photodiode PH and the transmission transistor area A2. In this state, when the transmission transistor 11 is turned off, a detection operation of the photodiode Ph is initiated at a point t1. When the detection operation is terminated and a detected signal charge is read out, a reset transistor GRX is turned off to isolate the floating diffusive node FD at a point t2. Then, the electric potential of the floating diffusive node FD is lowered. As a result, when the transmission transistor 11 is turned on at a point t3 the potential wall at the boundary surface K between the photodiode PH and the transmission transistor 11 becomes an amount “w1+w2” higher than in a reset state, that is, a case indicated by the solid line n1. (The electric potential at the point t3 is shown by a dotted line n2 of FIG. 2.) Thus, when the transmission transistor 11 is turned on to read out signal data, charges generated in the initial state remain in the photodiode area A1 until the electric potential of the photodiode Ph becomes an amount “w1+w2”. That is, the dead region of a pixel continues.
FIG. 3 is another timing diagram of driving an image sensor using the 4-transistor CMOS active pixel. Referring to FIG. 3, a convention method of driving an image sensor using a 4-transistor CMOS active pixel is described below. First, as a transmission control signal TX in a section T11 is deactivated (t11), a collection node that is a port at the N side of the photodiode PH is electrically separated from an external power voltage. In a section T12, the photodiode PH collects signal charges generated in response to light at the collection node. In a section T13, when a reset control signal RX is deactivated as “low” (t12) and a sampling signal SH is primarily activated (SH1), a voltage level of a data line that is an output port of an active pixel is sampled. The voltage level of the sampled data line is a voltage dropped by a predetermined drop voltage from a voltage of the floating diffusive node FD that is a reset level vrst. The drop voltage indicates a threshold voltage of a driving transistor which is gated by the floating diffusive node FD.
In a section T14, during which the transmission control signal TX is activated as “pulse” (t13), the charges at the collection node are transferred to the floating diffusive node FD. Thus, the voltages at the floating diffusive node and the collection node become a data level vdat generated by a charge sharing phenomenon. Then, the voltage level of the data line is sampled in response to a second activating pulse SH2 of the sampling signal SH. The voltage of the sampled data line becomes a voltage dropped by the drop voltage from the voltage at the floating diffusive node that is the data level vdat, like the reset level.
Consequently, a difference between the voltage levels of data lines sampled by the first activation SH1 and the second activation SH2 of the sampling signal SH is the same as a difference (vrst-vdat) between the reset level vrst and the data level vdat.
However, according to the conventional method of driving an active pixel of an image sensor, the reset level vrst is a voltage dropped by a first threshold voltage VT1 from the external power voltage VDD. The first threshold voltage VT1 is a threshold voltage of a reset transistor which is gated by the reset control signal RX and electrically connects the floating diffusive node FD to an external power voltage port. The initial voltage of the collection node is a voltage dropped from the external power voltage VDD by a value which is greater between the first threshold voltage VT1 and the second threshold voltage VT2. The second threshold voltage VT2 is a threshold voltage of the transmission transistor which is gated by the transmission control signal TX and connects the collection node to the floating diffusive node.
According to general image sensor design and manufacturing processes, a case in which the second threshold voltage VT2 is greater than the first threshold voltage VT1 occurs. In this case, while the reset level vrst is determined by the first threshold voltage VT1, the initial voltage of the collection node is determined by the second threshold voltage VT2.
A considerable deviation may occur in the first threshold voltage VT1 and the second threshold voltage VT2 according to the image sensor manufacturing process. As a result, the difference between the initial voltage at the collection node and the reset level vrst becomes irregular.
In the conventional method of reading out data of an image sensor by using the correlated double sampling method, the difference between the initial voltage at the collection node and the reset level vrst becomes irregular so that a low brightness feature of the image sensor is deteriorated.